In the integrated circuit field, scan testing involves introducing sequences of ones and zeros, called scan bits, into the integrated circuits for testing them. Scan compression is a way of reducing the volume of such bits sent from the tester to an integrated circuit.
Scan compression is mainstream technology today. A Glossary is provided in TABLE 1.
Scan compression architectures have components called a Compactor, STUMPs, and Decompressor. A Decompressor decompresses input channel data into internal scan-ins to multiple internal scan chains called STUMPs. (A respective scan channel pertains to any given set of scan chains among a number of such sets that make up all the scan chains in the integrated circuit.) There are different decompressor architectures available in the industry, e.g. XOR decompressor, mux/demux decompressor, LFSR (Linear Feedback Shift Register) based decompressor. A Compactor, also called a Compressor, compresses internal scan-outs data into output channels. Different compressor architectures are available in the industry for e.g. XOR compressor, and MISR (Multiple Input Signature Register) based compressor. Control logic programmation can be done through ATPG, such as when control logic is getting input data from decompressor or from top level input channels, or through an external interface like a JTAG 1149 scan interface or an IEEE 1500 scan interface.
Scan compression techniques are widely used to contain the test application time and test data volume. Scan partitioning of a device under test (DUT) is used to contain test mode power dissipation.
With a large number of clock domains, ATPG is simplified if clock pulse generation logic is also merged into the DUT scan chains. An ATPG tool controls generation of clock pulses on a per pattern basis. Each such scan chain is referred to herein as a clock-control chain, clock register chain or clock chain. A clock shaper module with a finite state machine FSM control and clock-control chain is amenable to such ATPG. For large designs, an additional concern is the power dissipated during the scan test mode of operation. DUT partitioning is often desirable for ease of implementing sub-chips and integrating them into an SOC (system-on-chip). Besides, it also allows for coarse grain test mode power control, since different series and parallel operations on different partitions can be controlled through various test modes.
For a SoC with a large number of clock domains, the logic contained in different clock domains is often selectively targeted for fault excitation and fault propagation in each pattern generated by the ATPG tool. In this way, faults in logic in specific clock domains are detected by different sets of patterns. Two reasons for problems with this mode of operation are:
While the logic within a clock domain is timed to perform at the rated speed of the clock, the logic across clock domains is often not, since it is considered asynchronous, and is hence often timed for slow multi-cycle operation. This makes the ATPG tool generated pattern set targeting such logic ineffective if there are multiple different clocks controlling the logic inside and across the domains. This is because (i) if the pattern is applied at rated speed, the inter-clock domain logic will not operate correctly, and (ii) if the pattern is applied at lower speed, the intra-clock domain logic is under-tested. In either case, the clocks to the different domains cannot be applied together, and must therefore be applied selectively, depending upon which portion of the logic is being targeted for coverage in a particular pattern.
Often the different domains are segregated for reasons of (i) modular design, (e.g. an SOC with multiple IPs integrated therein, wherein each IP is treated as a different partition) or (ii) test mode power control, (e.g. an SOC is divided up into different partitions, wherein only one or few partitions are targeted in a given phase (run) of ATPG, and the entire SOC is hence covered in ATPG through multiple such phases).
In both the above cases, different sets of ATPG patterns use different clocks. The ATPG pattern generation process is, therefore, coupled with a clock control process. Note that an ATPG pattern consists of a Shift phase wherein all flop-flops in the active scan chains are shifted together and a Capture phase wherein the response of the circuit to the initialized values in the flip-flops (in the immediately preceding Shift phase) is captured. For stuck-at fault ATPG patterns, a single Capture clock is adequate since the timing is not critical and slow clock application is adequate. However, for transition fault ATPG patterns, two Capture clocks are applied with the interval between them corresponding to the time period between successive clocks in the functional (normal) mode of operation. Transition fault ATPG patterns are thus used to test the logic at its rated speed of operation. Two ways of providing for this coupling are: (i) The clock control is set statically before the start of each phase of ATPG. In this case, different ATPG runs are involved to target logic within different clock domains, as well as across them. (ii) The clock control is set dynamically for each pattern by making the register which controls the generation of the capture clocks part of the scan chains of the logic under test. In this case, a single ATPG run targets all intra-domain and inter-domain logic.
The clock control mechanism in (ii) above becomes complex when the SOC is divided into different partitions for reasons of modular design or for test mode power containment. This is because the clock control register may be residing in one partition while a given ATPG run is being targeted to generate patterns to cover the logic in another partition. Some ways of addressing this problem are needed.
Another problem in a SOC with multiple partitions and scan design is that it is easier to control the clock register in each partition. In that case, the clock register must be replicated in each partition together with the clock controller, i.e. the entire clock shaper module must be replicated, so a separate clock shaper is used for each partition. The selected shaper provides selective capture of clock pulses, as controlled during ATPG, for transition fault patterns.
This approach has some important drawbacks:    (a) Logic overhead due to replication of the clock shaper logic in every partition.    (b) Even if the same functional clock were used for different partitions, the clock tree must be regenerated inside each one of them. In other words use of functional clock across multiple partitions leads to multiple clock trees being generated.    (c) Since the clock shapers and generated clocks are independent across the partitions, synchronous paths between the logic residing across clock domains cannot be tested or cannot be tested at-speed, since the clock outputs from independent clock shapers cannot be synchronized.    (d) Common clock control required across different partitions being tested together results in more inefficient ATPG since more care-bits are now required to fill up the clock control register in the scan chains within each partition. Inability to provide the required number of care-bits further results in two or more separate pattern sets.
The alternate approach is to keep a clock control register outside any DUT scan chain. This register would be programmed once at the beginning of each phase of ATPG. The disadvantages are two-fold. (i) It is cumbersome to perform ATPG in an SOC with multiple clock domains, since apart from multiple ATPG runs, (each of which requires the clock register to be programmed separately—the number of such runs can be intractably large for SOCs with 100+ clock domains), it is now also difficult to ensure that all possible capture clock sequences have been enumerated before the ATPG phases are finalized. (ii) Process-wise, the tool can perform ATPG more efficiently if the option of selecting a particular clock sequence for a particular pattern set is left to the tool, as against the sequence being fixed, (which is the case when a particular pattern set is being generated in a particular phase of ATPG).
Solutions to any of these and other problems are desired and needed in this art.